1. Field of the Invention
The present invention relates to a self-aligned process for manufacturing phase change memory cells.
2. Description of the Related Art
As is known, phase change memories use a class of materials that have the property of switching between two phases having distinct electrical characteristics, associated to two different crystallographic structures of the material, and precisely an amorphous, disorderly phase and a crystalline or polycrystalline, orderly phase. The two phases are hence associated to resistivities of considerably different values.
Currently, the alloys of elements of group VI of the periodic table, such as Te or Se, referred to as chalcogenides or chalcogenic materials, can be used advantageously in phase change memory cells. The currently most promising chalcogenide is formed from an alloy of Ge, Sb and Te (Ge2Sb2Te5), which is now widely used for storing information on overwritable disks and has been also proposed for mass storage.
In the chalcogenides, the resistivity varies by two or more orders of magnitude when the material passes from the amorphous (more resistive) phase to the crystalline (more conductive) phase, and vice versa.
Phase change can be obtained by locally increasing the temperature. Below 150° C., both phases are stable. Starting from an amorphous state, and rising the temperature above 200° C., there is a rapid nucleation of the crystallites and, if the material is kept at the crystallization temperature for a sufficiently long time, it undergoes a phase change and becomes crystalline. To bring the chalcogenide back to the amorphous state it is necessary to raise the temperature above the melting temperature (approximately 600° C.) and then rapidly cool off the chalcogenide.
Memory devices exploiting the properties of chalcogenic material (also called phase change memory devices) have been already proposed.
In a phase change memory including chalcogenic elements as storage elements, a plurality of memory cells are arranged in rows and columns to form an array. Each memory cell is coupled to a respective selection element, which may be implemented by any switching device, such as a PN diode, a bipolar junction transistor or a MOS transistor, and includes a chalcogenic region of a chalcogenide material in contact with a resistive electrode, also called heater. A storage element is formed at a contact area between the chalcogenide region and the heater. The heater is connected to a conduction terminal of the selection element.
In fact, from an electrical point of view, the crystallization temperature and the melting temperature are obtained by causing an electric current to flow through the resistive electrode in contact or close proximity with the chalcogenic material and thus heating the chalcogenic material by Joule effect.
In particular, when the chalcogenic material is in the amorphous, high resistivity state (also called the reset state), it is necessary to apply a voltage/current pulse of a suitable length and amplitude and allow the chalcogenic material to cool slowly. In this condition, the chalcogenic material changes its state and switches from a high resistivity to a low resistivity state (also called the set state).
Vice versa, when the chalcogenic material is in the set state, it is necessary to apply a voltage/current pulse of suitable length and high amplitude so as to cause the chalcogenic material to switch to the amorphous phase.
Several processes for manufacturing phase change memory cells and devices have been proposed so far, which, however, suffer from some limitations. In particular, known methods normally require several separate alignment steps to form the selection elements, the heaters, the chalcogenic regions and contacts for connecting the selection elements and the storage elements to word lines and bit lines.
In fact, the heaters are first aligned on conduction contacts of respective selection elements. Since minimization of the contact area between the heaters and the chalcogenic regions is a primary requirement in phase change memory cells, the heaters are normally in the form of walls or rods having sublithographic cross dimensions, i.e., thickness or diameter (“sublithographic” means here a linear dimension smaller than the minimum dimension achievable with current UV lithographic techniques, and hence smaller than 100 nm, down to approximately 5-20 nm). Structures having such a small dimension are made by controlled layer deposition steps. Thus, fabrication of the heaters includes depositing a dielectric layer on the conduction contacts, forming respective separate apertures in the dielectric layer on each conduction contact and aligned therewith, depositing a thin (sublithographic) layer of resistive material and possibly filling the apertures by a further dielectric material.
Then, a special mold layer is formed, having slits of sublithographic width on and across the heaters. The slits are filled by depositing a chalcogenic layer to make the storage elements. Hence, forming the mold layer uses a second alignment step.
A third alignment step is used to shape the chalcogenic layer and define resistive bit lines which connect storage elements arranged along the same array column.
Finally, bit lines, word line plugs and word lines are formed. The word line plugs must be aligned with control contacts of respective selection elements and the conductive bit lines are to be formed on resistive bit lines. Thereby, a fourth separate alignment step is involved.
Alignment of the heaters, of the resistive bit lines and of the word line plugs is particularly critical, because the effect of repeated alignment errors may lead to short circuits. As a result, an additional safety margin must be provided for and the cell area, as well as the array density, may not be optimized.